The thesis comprises three parts: Part 1 is the design and implementation of a high speed pipelined carry lookahead adder (CLA) ; Part 2 introduces how to build 0.35£gm basic cell library in the Cadence 97¡¦s environment and execute the cell-based design flow by self-built basic cells; Part 3 is the design and implementation of a low-power discrete cosine transform (DCT) processor.
Part 1 of this thesis is a 32-bit tree-structured pipelined carry lookahead adder (CLA) constructed by the modified all-N-transistor (ANT) design. Not only the CLA possesses few transistor count, but also occupies small chip size. Moreover, the post- layout simulation results given by TimeMill show that the clock used in the 32-bit CLA can run up to 1.25 GHz. The proposed architecture can be easily expanded for long data addition.
Part 2 of this thesis is to describe the procedure of a self-built cell library in detail, and explain how to correctly proceed cell-based design flow by using the self-built basic cell library.
Part 3 of this thesis is to implementation of a DCT processor. We carefully observed the operation behavior of Multiply Accumulator (MAC) and improved the power consumption
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0614101-230031 |
| Date | 14 June 2001 |
| Creators | Lee, Rong-Chin |
| Contributors | Chenn-Jung Huang, Sying-Jyan Wang, I.-J.Huang, Chau-Chin Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614101-230031 |
| Rights | restricted, Copyright information available at source archive |
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