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FPGA-Based Implementation of QR Decomposition

abstract: This thesis report aims at introducing the background of QR decomposition and its application. QR decomposition using Givens rotations is a efficient method to prevent directly matrix inverse in solving least square minimization problem, which is a typical approach for weight calculation in adaptive beamforming. Furthermore, this thesis introduces Givens rotations algorithm and two general VLSI (very large scale integrated circuit) architectures namely triangular systolic array and linear systolic array for numerically QR decomposition. To fulfill the goal, a 4 input channels triangular systolic array with 16 bits fixed-point format and a 5 input channels linear systolic array are implemented on FPGA (Field programmable gate array). The final result shows that the estimated clock frequencies of 65 MHz and 135 MHz on post-place and route static timing report could be achieved using Xilinx Virtex 6 xc6vlx240t chip. Meanwhile, this report proposes a new method to test the dynamic range of QR-D. The dynamic range of the both architectures can be achieved around 110dB. / Dissertation/Thesis / M.S. Electrical Engineering 2014

Identiferoai:union.ndltd.org:asu.edu/item:24870
Date January 2014
ContributorsYu, Hanguang (Author), Bliss, Daniel W (Advisor), Ying, Lei (Committee member), Chakrabarti, Chaitali (Committee member), Arizona State University (Publisher)
Source SetsArizona State University
LanguageEnglish
Detected LanguageEnglish
TypeMasters Thesis
Format96 pages
Rightshttp://rightsstatements.org/vocab/InC/1.0/, All Rights Reserved

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