A metal-insulator-semiconductor (MIS) device with a trilayer insulator structure consisting of sputtered SiO₂ (~50nm)/evaporated pure germanium (Ge) layer (2.4nm)/rapid thermal oxide (~5nm) was fabricated on a p-type Si substrate. The MIS device was rapid thermal annealed at 1000°C. Capacitance-voltage (C-V) measurements showed that, after rapid thermal annealing at 1000°C for 300s in Ar, the trilayer device exhibited charge storage property. The charge storage effect was not observed in a device with a bilayer structure without the Ge middle layer. With increasing rapid thermal annealing time from 0 to 400s, the width of the C-V hysteresis of the trilayer device increased significantly from 1.5V to ~11V, indicating that the charge storage capability was enhanced with increasing annealing time. High-resolution transmission electron microscopy results confirmed that with increasing annealing time, the 2.4nm amorphous middle Ge layer crystallized gradually. More Ge nanocrystals were formed and the crystallinity of the Ge layer improved as the annealing time was increased. When the measurement temperature was increased from –50°C to 150°C, the width of the hysteresis of the MIS device reduced from ~10V to ~6V. This means that the charge storage capability of the trilayer structure decreases with increasing measurement temperature. This is due to the fact that the leakage current in the trilayer structure increases with increasing measurement temperature. / Singapore-MIT Alliance (SMA)
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/3969 |
| Date | 01 1900 |
| Creators | Heng, C.L., Choi, Wee Kiong, Chim, Wai Kin, Teo, L.W., Ho, Vincent, Tjiu, W.W., Antoniadis, Dimitri A. |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | en_US |
| Detected Language | English |
| Type | Article |
| Format | 354001 bytes, application/pdf |
| Relation | Advanced Materials for Micro- and Nano-Systems (AMMNS); |
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