During the design and verification of the Hyperstone S5 flash memory controller, we
developed a highly effective way to use the SystemVerilog direct programming interface
(DPI) to integrate an instruction set simulator (ISS) and a software debugger in logic
simulation. The processor simulation was performed by the ISS, while all other hardware
components were simulated in the logic simulator. The ISS integration allowed us to filter
many of the bus accesses out of the logic simulation, accelerating runtime drastically. The
software debugger integration freed both hardware and software engineers to work in their
chosen development environments. Other benefits of this approach include testing and
integrating code earlier in the design cycle and more easily reproducing, in simulation,
problems found in FPGA prototypes.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:18736 |
| Date | 08 June 2007 |
| Creators | Freitas, Arthur |
| Contributors | Hardt, Wolfram |
| Publisher | Technische Universität Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | urn:nbn:de:swb:ch1-200700815, qucosa:18723 |
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