Return to search

Design of a hardware efficient key generation algorithm with a VHDL implementation /

Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/31442962
Date January 1993
CreatorsGoeke, James A.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceOnline version of thesis

Page generated in 0.0018 seconds