With the growing size of modern integrated circuit designs, automated design tools have taken an important role in the development flow. Through the use of these tools, designers can develop circuits in a robust and systematic manner. However, due to the high complexity of the designs and strict resource constraints, it is inevitable that mistakes will be made during the design process. Today, a significant amount of development time is dedicated to pre- and post-silicon verification and debug, which can increase the production cost and jeopardize the future growth of the industry. Hence, there is an urgent need for scalable automated verification and debugging techniques, as well as new methodologies that improve circuits in order to reduce errors. This dissertation presents a set of methodologies to automate three important processes in the VLSI design flow that are related to improving the quality of designs. The first contribution, automated logic restructuring, is a systematic methodology used to devise transformations in logic designs. This technique can be used for a wide range of post-synthesis applications, such as logic optimization, debugging and engineer change orders, which modify synthesized designs to accommodate their goals. Better results can be achieved if there are various transformations for those applications to select. Experiments demonstrate that the proposed technique is capable of re-structuring designs at a location where other methods fail and also identifies multiple transformations for each location. The second contribution is a logic-level, technology-independent soft error rate mitigation technique. Soft errors are transient logic pulses induced by radiation from the environment or released from the silicon chip package materials. This technique identifies conditions where soft errors can cause discrepancies at the primary outputs of the design, and eliminates those conditions through wire replacement. Experimental results confirm the effectiveness of the proposed technique and show that the soft error rate can be reduced at no or small additional overhead to other design parameters. The final contribution of the dissertation is a software environment for post-silicon debug. The proposed algorithms analyze the data collected during operating silicon chips at speed in the test system and provide useful information to expedite the debugging process. Experiments show that the proposed techniques eliminate one third of design modules, which are suspected as the root cause of the failure. Such a reduction can save engineers time on manual inspection and shorten the turnaround time of silicon debug.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/26264 |
| Date | 17 February 2011 |
| Creators | Yang, Yu-Shen |
| Contributors | Veneris, Andreas |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.0019 seconds