The imperfections in the semiconductor fabrication process and uncertainty in operating environment of VLSI circuits have emerged as critical challenges for the semiconductor industry. These are generally termed as process and environment variations, which lead to uncertainty in
performance and unreliable operation of the circuits. These problems have been
further aggravated in scaled nanometer technologies due to increased process
variations and reduced operating voltage.
Several techniques have been proposed recently for designing digital VLSI circuits
under variability. However, most of them have targeted ASICs and custom designs.
The flexibility of reconfiguration and unknown end application in FPGAs
make design under variability different for FPGAs compared to
ASICs and custom designs, and the techniques proposed for ASICs and custom designs cannot be directly applied
to FPGAs. An important design consideration is to minimize the modifications in architecture and circuit
to reduce the cost of changing the existing FPGA architecture and circuit.
The focus of this work can be divided into three principal categories, which are, improving
timing yield under process variations, improving power yield under process variations and improving the voltage profile
in the FPGA power grid.
The work on timing yield improvement proposes routing architecture enhancements along with CAD techniques to
improve the timing yield of FPGA designs. The work on power yield improvement for FPGAs selects a low power dual-Vdd FPGA design
as the baseline FPGA architecture for developing power yield enhancement techniques. It proposes CAD techniques to improve the
power yield of FPGAs. A mathematical programming technique is proposed to determine the parameters
of the buffers in the interconnect such as the sizes of the transistors and threshold voltage of the transistors, all
within constraints, such that the leakage variability is minimized under delay constraints.
Two CAD techniques are investigated and proposed to improve the supply voltage profile of
the power grids in FPGAs. The first technique is a place and route technique and the second technique
is a logic clustering technique to reduce IR-drops and spatial variation of supply voltage in the power grid.
| Identifer | oai:union.ndltd.org:WATERLOO/oai:uwspace.uwaterloo.ca:10012/5468 |
| Date | January 2010 |
| Creators | Kumar, Akhilesh |
| Source Sets | University of Waterloo Electronic Theses Repository |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
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