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Current mode logic latch and prescaler design optimization in 0.18um CMOS technology /

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references. Also available in electronic format on the Internet.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/290726513
Date January 1900
CreatorsUsama, Muhammad,
PublisherOttawa:
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceProQuest Full Text

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