This dissertation presents an approach to generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model and detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a Process Model Graph (PMG). A set of VHDL functions have been constructed to help develop VHDL models. Two algorithms are proposed to implement the test generation. <b>P-Algorithm</b> is used to generate tests at the process level. For each process a symbolic test set and the corresponding fixed valued test packages (FVTPs) are generated. Synthesis-related FVTP generation algorithms for the VHDL functions are derived to support the P-algorithm. <b>E-Algorithm</b> is employed to generate the entity level tests. The symbolic entity level tests are generated first and then the final fixed valued entity level tests are obtained by calculating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The HILO fault grader is used to generate fault coverage. Several conversion programs have been developed to support the test evaluation. / Ph. D.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/39466 |
| Date | 23 September 2008 |
| Creators | Li, Wencheng |
| Contributors | Electrical Engineering, Armstrong, James R., Balci, Osman, Gray, F. Gail, Cyre, Walling R., Athanas, P.M. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Dissertation, Text |
| Format | x, 176 leaves, BTD, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 35301092, LD5655.V856_1996.L5.pdf |
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