The aim of this thesis was to design and implement PCI Express Bridge. The main purpose of this unit is to help application engineers who develop various FPGA based accelerators. The implemented unit transforms complex PCI Express based system bus interface to more common and scalable interface of internal bus for on-chip components interconnection. This allows engineers to focus on the development of their target applications, not on a complicated communication protocol. The unit was implemented in the VHDL language, synthesized for Virtex-5 based FPGAs as well as completely tested on ML555 and COMBOv2 cards. The acquired results show that the component reaches the throughput of 7 Gb/s, which is the theoretical limitation of underlying protocols.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:236738 |
| Date | January 2009 |
| Creators | Korček, Pavol |
| Contributors | Kořenek, Jan, Martínek, Tomáš |
| Publisher | Vysoké učení technické v Brně. Fakulta informačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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