In wireless communication system, convolution code has been one of the most popular error-correcting code. To prevent from the interference of noise during transmission, the transmitter usually applies convolution encode to code the processed information, and the receiver will use Viterbi decoder to decode and correct the error bit to decrease the bit error rate. In 3G mobile communication, such decoder is often applied between the base station and the communication device as a decoding mechanism. Since traditional decoders of communication devices consume more than one third power of the whole receiver, the present study focuses on the way effectively reducing the power consumption of Viterbi decoder.
Traditional convolution coders use zero-tail, which make decoder be able to resist the interference of noise; however, this method would increase extra tail bits, which would decrease the code rate and affect the efficiency of transmission, especially for those information with short length, such as the header of packet. Tail-biting convolution code is another error-correcting code, which maintains the code rate, and it has been used in the control channel of LTE. Tail-biting convolution code is more complex than traditional decoder. Therefore, this thesis modifies the Wrap-Around Viterbi Algorithm (WAVA) to enormously decrease the power consuming while maintaining the bit error rate and the correctness of decoding. The aim of the present study is achieved by decreasing iteration number of WAVA algorithm to reduce one fourth of the whole power consumption.
On the other hand, if the received information is not interfered by noise, it¡¦s unnecessary to turn on Tail-biting Convolution Decoder. As a result, the present study introduces the error detection circuit so that the received information can be simply decode and detected with the error detection circuit. If there is no noise interference, it can directly be outputted; if there is noise interference, however, it should be decoded by Tail-biting Convolution Decoder.
The experimental results show that the survivor memory unit saves more than 60% power than traditional decoders, moreover, it will save 55%~88% power consumption when it goes with the error detection circuit. Consequently, the proposed method is indeed able to reduce the power consumption of Tail-biting Convolution Decoder.
Keyword¡Gwireless communication, tail-biting convolution code, code rate, Viterbi decoder, power consumption
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0725112-101332 |
| Date | 25 July 2012 |
| Creators | Tseng, I-Ping |
| Contributors | Jer-Min Jou, Shiann-Rong Kuang, Tso-Bing Juang, Shen-Fu Hsiao, Yun-Nan Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-101332 |
| Rights | user_define, Copyright information available at source archive |
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