In this dissertation, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying four new common-subexpression-elimination (CSE) algorithms to the sub-functions that realize the various transformations in AES encryption and decryption. The first category of sub-functions is derived by combining adjacent transformations in each AES round into a new transformation. The other category of sub-functions is from the integrated transformations in the AES encryption and decryption process with shared common operations. Then the proposed bit-level CSE algorithm reduces further the area cost of realizing the sub-functions by extracting the common factors in the bit-level expressions of these sub-functions. The separate area-reduction effects of combinations, integrations and CSE optimization mentioned above are analyzed in order to examine the efficiency of each technique. Cell-based implementation results show that the area reduction rates of the AES processors with our proposed CSE methods achieve significant area improvement compared with Synopsys optimization results.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-1005105-143759 |
| Date | 05 October 2005 |
| Creators | Chen, Ming-Chih |
| Contributors | Bin-Da Liu, Ming-Hwa Sheu, Chua-Chin Wang, Jiun-In Guo, Shen-Fu Hsiao, Jau-Der Shih |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1005105-143759 |
| Rights | campus_withheld, Copyright information available at source archive |
Page generated in 0.0017 seconds