This thesis deals with utilizing C2H technique for implementation algorithm on FPGA. Several structures of digital filters FIR and IIR are implemented within this work with usage of C2H. For such a comparison is in terms of FPGA resources utilized, the maximum frequency, latency, complexity of implementation and acceleration obtained to Nios II processor itself. Example for image processing using local operators implemented using C2h is also created to display the result on the LCD.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219681 |
| Date | January 2012 |
| Creators | Otisk, Libor |
| Contributors | Bastl, Petr, Valach, Soběslav |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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