Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, requires high performance I/O links to achieve a per pin data rate as high as multi-Gb/s. The design of high-speed links employing forwarded-clock architecture enables jitter tracking between data and clock from low to high frequencies. Considering the impact of clock to data skew, high frequency sampling clock jitter and data jitter become out of phase at receiver, which reduces the timing margin and limits the data rate. The jitter tracking bandwidth (JTB) between data and clock should be optimized to compensate the clock to data skew. System level analysis shows that the wide tunable range of JTB is needed to compensate different amounts of skews.
The implementation of bandpass filtering on forwarded-clock path is able to control the JTB through the controlling of Q. This work introduces a method using bandpass filtering to optimize the JTB in high-speed forwarded-clock transceivers, followed by the implementation of active-inductor-based bandpass filter as clock receiver, which has advantages of low-voltage operation, low power as well as low area consumption. Simulation results shows that the designed filter provides controllable JTB over 40 - 600MHz. The bandpass filter is implemented in IBM 90nm CMOS process.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2011-05-9434 |
| Date | 2011 May 1900 |
| Creators | Liu, Yang |
| Contributors | Palermo, Samuel |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | thesis, text |
| Format | application/pdf |
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