Advances in CMOS technology have resulted in increased clock fre-quencies, even exceeding 3GHz. At the same time, frequencies on most board wires are 125-800MHz. It is especially problematic in modern computer mem-ory buses and high speed telecommunication devices, such as switches and routers operating at 10Gb/s on its ports. It is believed that circuit board buses can be used up to about 20GHz, but there is a problem with Intersymbol Inter-ference (ISI) causing distortion of transmitted symbols by multiple reflections. Actually, the circuit board bus behaves like a passive low pass filter with unknown (perhaps changing) transfer characteristic. The problem of ISI was solved some time ago in the telecommunication area. With use of adaptive equalizers it is possible to increase throughput of a long distance communication channel dramatically. But the microprocessor bus has certain differences from telecommunica-tion devices such as modems. First of all, the clock frequency on a bus is much higher than in modems. Secondly, a bus has a much more complex structure than a telecommunication channel. At the same time, we can’t use a lot of re-sources for bus maintaining. The aim of the thesis work is to investigate the possibility of using adap-tive equalization on a bus, and the construction of a reasonable mathematical model of such an equalizer. Also limits of equalizationare examined and de-pendencies are derived.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-1466 |
| Date | January 2002 |
| Creators | Guzeev, Andrew |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | LiTH-ISY-Ex, ; 3306 |
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