In this thesis we discuss design and implementation of low-complexity digital filters. Digital filters are key components in most digital signal processing (DSP) systems and are, for example, used for interpolation and decimation. A typical application for the filters considered in this work is mobile communication systems, where high throughput and low power consumption are required. In the first part of the thesis we discuss implementation of high throughput lattice wave digital filters (LWDFs). Here arithmetic transformation of first- and second-order Richards’ allpass sections are proposed. The transformations reduces the iteration period bound of the filter realization, which can be used to increase the throughput or reduce the power consumption through power supply voltage scaling. Implementation of LWDFs using redundant, carry-save arithmetic is considered and the proposed arithmetic transformations are evaluated with respect to throughput and area requirements. In the second part of the thesis we discuss three case studies of implementations of digital filters for typical applications with requirements on high throughput and low power consumption. The first involves the design and implementation of a digital down converter (DDC) for a multiple antenna element radar receiver. The DDC is used to convert a real IF input signal into a complex baseband signal composed of an inphase and a quadrature component. The DDC includes bandpass sampling, digital I/Q demodulation, decimation, and filtering and three different DDC realizations are proposed and evaluated. The second case study is a combined interpolator and decimator filter for use in an OFDM system. The analog-to-digital converters (ADCs) and the digital-to-analog converters (DACs) work at a sample rate twice as high as the Nyquist rate. Hence, interpolation and decimation by a factor of two is required. Also, some channel shaping is performed which complicates the filter design as well as the implementation. Frequency masking techniques and novel filter structures was used for the implementation. The combined interpolator and decimator was successfully implemented using an LWDF in a 0.35 mm CMOS process using carry-save arithmetic. The third case study is the implementation of a high-speed decimation filter for a SD ADC. The decimator has an input data rate of 16 Gsample/s and the decimation factor is 128. The decimation is performed using two cascaded digital filters, a comb filter followed by a linear-phase FIR filter. A novel hardware structure for single-bit input digital filters is proposed. The proposed structure was found to be competitive and was used for the implementation. The decimator filter was successfully implemented in a 0.18 mm CMOS process using standard cells. In the third part of the thesis we discuss efficient realization of sum-of-products and multiple-constant multiplications that are used in, for example, FIR filters. We propose several new difference methods that result in realizations with a low number of adders. The proposed design methods have low complexity, i.e., they can be included in the search for quantized filter coefficients.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-5063 |
| Date | January 2005 |
| Creators | Ohlsson, Henrik |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Doctoral thesis, monograph, info:eu-repo/semantics/doctoralThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | Linköping Studies in Science and Technology. Dissertations, 0345-7524 ; 949 |
Page generated in 0.002 seconds