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Developing a Neural Signal Processor Using the Extended Analog Computer

Indiana University-Purdue University Indianapolis (IUPUI) / Neural signal processing to decode neural activity has been an active research area in the last few decades. The next generation of advanced multi-electrode neuroprosthetic devices aim to detect a multiplicity of channels from multiple electrodes, making the relatively time-critical processing problem massively parallel and pushing the computational demands beyond the limits of current embedded digital signal processing (DSP) techniques. To overcome these limitations, a new hybrid computational technique was explored, the Extended Analog Computer (EAC). The EAC is a digitally confgurable analog computer that takes advantage of the intrinsic ability of manifolds to solve partial diferential equations (PDEs). They are extremely fast, require little power, and have great potential for mobile computing applications.

In this thesis, the EAC architecture and the mechanism of the formation of potential/current manifolds was derived and analyzed to capture its theoretical mode of operation. A new mode of operation, resistance mode, was developed and a method was devised to sample temporal data and allow their use on the EAC. The method was validated by demonstration of the device solving linear diferential equations and linear functions, and implementing arbitrary finite impulse response (FIR) and infinite impulse response (IIR) linear flters. These results were compared to conventional DSP results. A practical application to the neural computing task was further demonstrated by implementing a matched filter with the EAC simulator and the physical prototype to detect single fiber action potential from multiunit data streams derived from recorded raw electroneurograms. Exclusion error (type 1 error) and inclusion error (type 2 error) were calculated to evaluate the detection rate of the matched filter implemented on the EAC. The detection rates were found to be statistically equivalent to that from DSP simulations with exclusion and inclusion errors at 0% and 1%, respectively.

Identiferoai:union.ndltd.org:IUPUI/oai:scholarworks.iupui.edu:1805/3452
Date21 August 2013
CreatorsSoliman, Muller Mark
ContributorsYoshida, Ken, Eberhart, Russell C., Mills, Jonathan W. (Jonathan Wayne), Berbari, Edward J.
Source SetsIndiana University-Purdue University Indianapolis
Languageen_US
Detected LanguageEnglish
TypeThesis

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