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Applying the "split-ADC" architecture to a 16 bit, 1 MS/s differential successive approximation analog-to-digital converter

Thesis (M.S.)--Worcester Polytechnic Institute. / Keywords: error correction, calibration, successive approximation. Includes bibliographical references (leaves 89-91).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/228030083
Date January 2008
CreatorsChan, Ka Yan.
PublisherWorcester, Mass. : Worcester Polytechnic Institute,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceLink to electronic thesis

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