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20-stage pipelined ADC with radix-based calibration

A radix-based calibration technique was previously proposed with a two-stage
algorithmic analog-to-digital converter (ADC). The objective of this work is to verify
the capability of radix-based calibration for a true multi-stage ADC. In order to prove
the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-��m
CMOS technology. The system is fully differential and requires two non-overlapping
clock phases to operate. The implementation of the calibration technique in the
pipelined ADC is investigated. Simulation results show that 109dB of SNDR,
112dB of THD, and 116dB of SFDR can be achieved, which indicates the overall
accuracy of the ADC is 18 bits. / Graduation date: 2003

Identiferoai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/32132
Date07 November 2002
CreatorsYun, Chong Kyu
ContributorsMoon, Un-Ku
Source SetsOregon State University
Languageen_US
Detected LanguageEnglish
TypeThesis/Dissertation

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