IP vendors need to keep the internal designs of their IP secret from the IP user for security or commercial reasons. The CAD tools provided by FPGA vendors have some built-in functionality to encrypt the IP. However, the IP is consequently decrypted by the CAD tools in order to run the IP through the design flow. An IP user can use APIs provided by the CAD tools to recreate the IP in an unencrypted state. An IP user could also easily learn the internals of a protected IP with the advent of new open-source bitstream to netlist tools. The user can simply generate a bitstream that includes the protected IP and then use the tools to create a netlist of the third party IP, exposing the internals of IP. Any solution to keep IP protected must keep the IP encrypted through the CAD tools and bitstream generation all the way to FPGA configuration. This thesis presents a design methodology, along with a proof-of-concept tool, that demonstrates how IP can remain partially encrypted through the CAD flow and into the bitstream. It shows how this approach can support multiple encryption keys from different vendors, and can be deployed using existing CAD tools and FPGA families. Results are presented that document the benefits and costs of using such an approach to provide much greater protection for 3rd party IP.
| Identifer | oai:union.ndltd.org:BGMYU2/oai:scholarsarchive.byu.edu:etd-11100 |
| Date | 14 August 2023 |
| Creators | Hutchings, Daniel |
| Publisher | BYU ScholarsArchive |
| Source Sets | Brigham Young University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Theses and Dissertations |
| Rights | https://lib.byu.edu/about/copyright/ |
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