by Cheang Sin Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1990. / Bibliography: leaves 137-140. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.ii / TABLE OF CONTENTS --- p.iii / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Lisp as an AI Programming Language --- p.1 / Chapter 1.2 --- Assisting List Processing with Hardware --- p.2 / Chapter 1.3 --- Simulation Study --- p.2 / Chapter 1.4 --- Implementation --- p.3 / Chapter 1.4.1 --- Hardware --- p.3 / Chapter 1.4.2 --- Software --- p.3 / Chapter 1.5 --- Performance --- p.4 / Chapter CHAPTER 2 --- LISP AND EXISTING LISP MACHINES --- p.5 / Chapter 2.1 --- Lisp and its Internal Structure --- p.5 / Chapter 2.1.1 --- The List Structure in Lisp --- p.5 / Chapter 2.1.2 --- Data Types in Lisp --- p.7 / Chapter 2.1.3 --- Lisp Functions --- p.8 / Chapter 2.1.4 --- Storage Management of Lisp --- p.9 / Chapter 2.2 --- Existing Lisp Machines --- p.11 / Chapter 2.2.1 --- Types of AI Architecture --- p.11 / Language-Based architecture --- p.11 / Knowledge-Based architecture --- p.12 / Semantic networks --- p.12 / Chapter 2.2.2 --- Lisp Machines --- p.12 / Solving problems of Lisp --- p.13 / Chapter 2.2.3 --- Classes of Lisp Machines --- p.14 / Two M Lisp machine examples --- p.15 / A class P machine example --- p.17 / A class S machine example --- p.17 / The best class for Lisp --- p.19 / Chapter 2.3 --- Execution Time Analysis of a Lisp System --- p.20 / Chapter 2.3.1 --- CPU Time Statistics --- p.20 / Chapter 2.3.2 --- Statistics Analysis --- p.24 / Chapter CHAPTER 3 --- OVERALL ARCHITECTURE OF THE ASLP --- p.27 / Chapter 3.1 --- An Arithmetical & Symbolical List Processor --- p.27 / Chapter 3.2 --- Multiple Memory Modules --- p.30 / Chapter 3.3 --- Large Number of Registers --- p.31 / Chapter 3.4 --- Multiple Buses --- p.34 / Chapter 3.5 --- Special Function Units --- p.35 / Chapter CHAPTER 4 --- PARALLELISM IN THE ASLP --- p.36 / Chapter 4.1 --- Parallel Data Movement --- p.36 / Chapter 4.2 --- Wide Memory Modules --- p.37 / Chapter 4.3 --- Parallel Memory Access --- p.39 / Chapter 4.3.1 --- Parallelism and Pipelining --- p.39 / Chapter 4.4 --- Pipelined Micro-Instructions --- p.40 / Chapter 4.4.1 --- Memory access pipelining --- p.41 / Chapter 4.5 --- Performance Estimation --- p.44 / Chapter 4.6 --- Parallel Execution with the Host Computer --- p.45 / Chapter CHAPTER 5 --- SIMULATION STUDY OF THE ASLP --- p.47 / Chapter 5.1 --- Why Simulation is needed for the ASLP? --- p.47 / Chapter 5.2 --- The Structure of the HOCB Simulator --- p.48 / Chapter 5.2.1 --- Activity-Oriented Simulation for the ASLP --- p.50 / Chapter 5.3 --- The Hardware Object Declaration Method --- p.50 / Chapter 5.4 --- A Register-Level Simulation of the ASLP --- p.53 / Chapter 5.4.1 --- A List Function Simulation --- p.54 / Chapter CHAPTER 6 --- DESIGN AND IMPLEMENTATION OF THE ASLP --- p.57 / Chapter 6.1 --- Hardware --- p.57 / Chapter 6.1.1 --- Microprogrammable Controller --- p.57 / The instruction cycle of the micro-controller --- p.59 / Chapter 6.1.2 --- Chip Selection and Allocation --- p.59 / Chapter 6.2 --- Software --- p.61 / Chapter 6.2.1 --- Instruction Passing --- p.61 / Chapter 6.2.2 --- Microprogram Development --- p.62 / Microprogram field definition --- p.64 / Micro-assembly language --- p.65 / Macro-instructions --- p.65 / Down-loading of Micro-Codes --- p.66 / Interfacing to C language --- p.66 / A Turbo C Function Library --- p.67 / Chapter CHAPTER 7 --- PERFORMANCE EVALUATION OF THE ASLP …… --- p.68 / Chapter 7.1 --- Micro-Functions in the ASLP --- p.68 / Chapter 7.2 --- Functions in the C Library --- p.71 / Chapter CHAPTER 8 --- FUNCTIONAL EVALUATION OF THE ASLP --- p.77 / Chapter 8.1 --- A Relational Database on the ASLP --- p.77 / Chapter 8.1.1 --- Data Representation --- p.77 / Chapter 8.1.2 --- Performance of the Database System --- p.79 / Chapter 8.2 --- Other Potential Applications --- p.80 / Chapter CHAPTER 9 --- FUTURE DEVELOPMENT OF THE ASLP --- p.81 / Chapter 9.1 --- An Expert System Shell on the ASLP --- p.81 / Chapter 9.1.1 --- Definition of Objects --- p.81 / Chapter 9.1.2 --- Knowledge Representation --- p.84 / Chapter 9.1.3 --- Knowledge Representation in the ASLP --- p.85 / Chapter 9.1.4 --- Overall Structure --- p.88 / Chapter 9.2 --- Reducing the Physical Size by Employing VLSIs --- p.89 / Chapter CHAPTER 10 --- CONCLUSION --- p.92 / Chapter APPENDIX A --- BLOCK DIAGRAM --- p.95 / Chapter APPENDIX B --- ASLP CIRCUIT DIAGRAMS --- p.97 / Chapter APPENDIX C --- ASLP PC-BOARD LAYOUTS --- p.114 / Chapter APPENDIX D --- MICRO-CONTROL SIGNAL ASSIGNMENT --- p.121 / Chapter APPENDIX E --- MICRO-FIELD DEFINITION --- p.124 / Chapter APPENDIX F --- MACRO DEFINITION --- p.133 / Chapter APPENDIX G --- REGISTER ASSIGNMENT --- p.134 / PUBLICATIONS --- p.136 / REFERENCES --- p.137
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_318608 |
| Date | January 1990 |
| Contributors | Cheang, Sin Man., Chinese University of Hong Kong Graduate School. Division of Computer Science. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, v, 140 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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