by Lin Hon Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 59-[63]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Organization of Thesis --- p.3 / Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Unicast Cross-Path switch --- p.5 / Chapter 2.2.1 --- Routing properties in Clos networks --- p.5 / Chapter 2.2.2 --- Quasi-static routing procedures --- p.5 / Chapter 2.2.3 --- Capacity and Route Assignment --- p.7 / Chapter 2.3 --- Multicast Cross-Path Switch --- p.8 / Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10 / Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10 / Chapter 3 --- Architectures --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16 / Chapter 3.2.1 --- Input Header Translator --- p.16 / Chapter 3.2.2 --- Input Module Controller --- p.17 / Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19 / Chapter 3.2.4 --- Routing Network --- p.23 / Chapter 3.3 --- Central Modules --- p.24 / Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24 / Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25 / Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26 / Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27 / Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28 / Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29 / Chapter 4 --- Performance Evaluations --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Traffic characteristics --- p.31 / Chapter 4.2.1 --- Fanout distribution --- p.31 / Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32 / Chapter 4.3 --- Throughput Performance --- p.34 / Chapter 4.4 --- Delay Performance --- p.37 / Chapter 4.4.1 --- Input Stage Delay --- p.38 / Chapter 4.4.2 --- Output Stage Delay --- p.39 / Chapter 4.5 --- Cell Loss Performance --- p.43 / Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44 / Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45 / Chapter 4.6 --- Complexities --- p.50 / Chapter 5 --- Conclusions --- p.57 / Bibliography --- p.59
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_322398 |
| Date | January 1998 |
| Contributors | Lin, Hon Man., Chinese University of Hong Kong Graduate School. Division of Information Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, ix, 59, [4] leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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