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Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning

This letter presents a scalable technique to reduce the power of the analog input stage in neural recording front-ends in Globalfoundries 22 -nm FDSOI. The back-gate voltages are adapted to reduce the threshold voltage and thus allow supply voltage reduction. This adaption increases PVT stability of subthreshold circuits. A comparison to a conventional delta–sigma ADC is drawn and the minimum power point is measured, resulting in 0.7 - μW /channel at 7.2 - μV input-referred noise. Additionally, the transition to smaller technologies promises low-power consumption in the digital domain, by allowing smaller supply voltage and higher integration density.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:90108
Date23 February 2024
CreatorsSchüffny, Franz Marcus, Höppner, Sebastian, Hänzsche, Stefan, George, Richard Miru, Zeinolabedin, Seyed Mohammad Ali, Mayr, Christian
ContributorsTechnische Universität Dresden
PublisherIEEE - Institute of Electrical and Electronics Engineers
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/acceptedVersion, doc-type:article, info:eu-repo/semantics/article, doc-type:Text
Rightsinfo:eu-repo/semantics/openAccess
Relation2573-9603, 10.1109/LSSC.2023.3270243, info:eu-repo/grantAgreement/European Commission/H2020 | RIA/824162//A SYnaptically connected brain-silicon Neural Closed-loop Hybrid system/SYNCH, info:eu-repo/grantAgreement/Bundesministerium für Bildung und Forschung/Souverän. Digital. Vernetzt./16KISK001K//6G-Life

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