The continuous growth of global demand for semiconductor products (in a broad range of sectors, such as security, healthcare, entertainment, connectivity, energy, etc.) has been both enabled and fuelled by Moore's law and regular doubling of circuit density and performance increases. However, as CMOS technology scaling begins to reach its theoretical limits, the ITRS predicts a new era known as "Beyond CMOS". Novel materials and devices show an ability to complement or even replace the CMOS transistor or its channel in systems on chip with silicon-based technology. This has led to the identification of promising phenomena such as ambipolar conduction in quasi one- and zero-dimensional structures, for example in carbon nanotubes, graphene and silicon nanowires. Ambipolarity, in a dual-gate context (DG-FETs), means that n- and p-type behavior can be observed in the same device depending on the backgate voltage polarity. In addition to their attractive performances and the low power consumption, ambipolar double gate devices enable the development of completely new circuit structures and design paradigms. Conventional logic synthesis techniques cannot represent the capability of DG-FETs to operate as either n-type or p-type switches and new techniques must be found to build optimal logic. The work in this thesis explores design techniques to enable the use of such devices by defining generic approaches and design techniques based on ambipolar DG-FETs. Two different contexts are tackled: (i) improving standard cell logic design with more compact structures and better performance, as well as low-power design techniques exploiting the fourth terminal of the device, and (ii) adapting conventional logic synthesis and verification techniques such as Binary Decision Diagrams or Function Classification to ambipolar DGFETs in order to build reconfigurable logic cells. The proposed methods and techniques are validated and evaluated in a case study focused on DG-CNTFET through accurate simulations, using the most mature and recent DG-CNTFET model available in the literature.
| Identifer | oai:union.ndltd.org:CCSD/oai:tel.archives-ouvertes.fr:tel-00777679 |
| Date | 11 September 2012 |
| Creators | Jabeur, Kotb |
| Publisher | Ecole Centrale de Lyon |
| Source Sets | CCSD theses-EN-ligne, France |
| Language | English |
| Detected Language | English |
| Type | PhD thesis |
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