In recent years there has been significant research in the field of computational neuroscience and many of these biologically inspired cognitive models are based on the theory of operation of mammalian visual cortex. One such model of neocortex developed by George & Hawkins, known as Hierarchical Temporal Memories (HTM), is considered for the research discussed here. We propose a simple hierarchical model that is derived from HTM. The aim of this work is to evaluate the hardware cost and performance against software based simulations. This work presents a detailed hardware implementation and analysis of the derived hierarchical model. We show that these networks are inherently parallel in their architecture, similar to the biological computing, and that parallelism can be exploited by massively parallel architectures implemented using reconfigurable devices such as the FPGA. Hardware implementation accelerates the learning process which is useful in many real world problems. We have implemented a complex network node that operates in real time using an FPGA. The current architecture is modular and allows us to estimate the hardware resources and computational units required to realize large scale networks in the future.
| Identifer | oai:union.ndltd.org:pdx.edu/oai:pdxscholar.library.pdx.edu:open_access_etds-1159 |
| Date | 01 January 2011 |
| Creators | Deshpande, Mandar |
| Publisher | PDXScholar |
| Source Sets | Portland State University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Dissertations and Theses |
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