<p> Over the past few decades, wireless communication systems have experienced rapid advances that demand continuous improvements in wireless transceiver architecture, efficiency and power capabilities. Since the most power consuming block in a transceiver is the power amplifier, it is considered one of the most challenging blocks to design, and thus, it has attracted considerable research interests. However, very little work has addressed low-power designs since most previous research work focused on higher power applications. Short-range transceivers are increasingly gaining interest with the emerging low-power wireless applications that have very strict requirements on the size, weight and power consumption of the system. </p> <p> This thesis deals with designing fully-integrated RF power amplifiers with low output power levels as a first step to improving the efficiency of RF transceivers in a 0.18 J.Lm standard CMOS technology. Two switch-mode power amplifiers, one operating at a frequency of 650 MHz and the other at a frequency of 2.4 GHz, are presented in this work using a class-E output stage with a class-F driver stage. The work presented here represents the first use of class-E power amplifiers for low-power applications. The measurement results of the 650 MHz design show a maximum drain efficiency of 15 % and a maximum gain of 11.5 dB. When operated from a 0.65 V supply, the power amplifier delivers an output power of 750 J.LW with a maximum power-added efficiency (PAE) of 10 %. As for the 2.4 GHz design, three layouts were fabricated. The first two designs have a filtered and a non-filtered output to show the effects of using on-chip filtering in low-power designs. Special attention was given to optimize the layout and minimize the parasitic effects. Measurement results show a maximum drain efficiency of 38 % and a maximum gain of 17 dB. When operating from a 1.2 V supply, the power amplifier delivers an output power of9 mW with a PAE of33 %. The supply voltage can go down to 0.6 V with an output power of2 mW and a PAE of25 %. The improvements in the layout show an increase in drain efficiency from 8 % to 35 %. The third design uses a 2 ~m thick top-metal layer of low-resistivity, with the same circuit component values as the first two designs. Measurement results show a maximum drain efficiency of 53 % and a maximum gain of 22 dB. When operating from a 1.2 V supply, the power amplifier delivers an output power of 14.5 mW with a PAE of 51 %. The supply voltage can go down to 0.6 V with an output power of 3.5 mW and a PAE of 43 %. </p> <p> Also, a novel mode-locking power amplifier design is presented in two fullyintegrated, differential superharmonic injection-locked power amplifiers (ILP A) operating at a frequency of 2.4 GHz and at a frequency of 400 MHz. Measurement results of the 2.4 GHz design and the 400 MHz design show that the fabricated power amplifiers have a maximum gain of 31 dB from only one stage that occupies a chip area of only 0.6 mm2 and 0.9 mm2 respectively, with all components fully integrated. </p> <p> Finally, two fully-integrated, single block baseband direct-modulation transmitters operating at a frequency of 2.4 GHz and at a frequency of 400 MHz are also presented in this work. Measurement results of the 2.4 GHz transmitter show a drain efficiency of 27 %. When operating from a 1.5 V supply, the transmitter delivers an output power of 8 dBm with a low phase noise of -122 dBc/Hz at a 1 MHz offset. </p> / Thesis / Master of Applied Science (MASc)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/21928 |
| Date | 01 1900 |
| Creators | El-Desouki, Munir |
| Contributors | Deen, M., Haddara, Yaser, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Language | English |
| Detected Language | English |
Page generated in 0.0016 seconds