This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a high-voltage, low-offset current sense amplifier, which achieves a common-mode input range that is within a Vtp of Vdd using a bulk-driven differential input stage. The amplifier also uses high voltage cascode devices to protect low-voltage devices that have been placed in critical matching areas to achieve a low input offset voltage of 500uV without the use of trim. A short to battery architecture is also discussed which uses a bulk-driven comparator and a PMOS blocking technique and allows for a reliable short to battery breakdown voltage without using a series blocking diode. Integration of these blocks into a standard CMOS process leads to cost savings as additional devices such as data converters and microprocessors are combined with the Hall-effect sensor interface.
| Identifer | oai:union.ndltd.org:BGMYU2/oai:scholarsarchive.byu.edu:etd-1808 |
| Date | 17 November 2005 |
| Creators | Beck, Riley D. |
| Publisher | BYU ScholarsArchive |
| Source Sets | Brigham Young University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Theses and Dissertations |
| Rights | http://lib.byu.edu/about/copyright/ |
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