Verifying that a hardware module connected to a bus follows the bus protocol correctly is a necessity in a bus-based System-on-Chip (SoC) development. Traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not, but they are non-synthesizable and thus could not identify bugs occurring at run time in real physical environment. We propose a rule-based and synthesizable protocol checker (HPChecker) for AMBA AHB Bus. It contains 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanisms to shorten debugging time. Error reference table can summarize the violation condition of a design under test (DUT); History Memory contains the content of violation signals. These two mechanisms can help designer debugging efficiently. The gate counts of the HPChecker are 43,432 gates and the speed of it is 203 MHz at 0.18Mm technology. Finally, the HPChecker has been integrated into a 3D graphics accelerator and successfully identifies protocol violation in the FPGA prototype. . HPChecker has been successfully licensed to industries in France and Taiwan to assist SoC development.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-1212107-202840 |
| Date | 12 December 2007 |
| Creators | Wang, Chien-chou |
| Contributors | Shian-Rong Kuang, Jih-Ching Chiu, Jin-Hua Hong, Ing-Jer Huang, Shu-Min Li |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1212107-202840 |
| Rights | restricted, Copyright information available at source archive |
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