The scaling of VLSI technology has spurred a rapid growth in the semiconductor
industry. With the CMOS device dimension scaling to and beyond 90nm technology,
it is possible to achieve higher performance and to pack more complex functionalities
on a single chip. However, the scaling trend has introduced drastic variation of
process and design parameters, leading to severe variability of chip performance in
nanometer regime. Also, the manufacturing community projects CMOS will scale for
three to four more generations. Since the uncertainties due to variations are expected
to increase in each generation, it will significantly impact the performance of design
and consequently the yield.
Another challenging issue in the nanometer IC design is the high power consumption
due to the greater packing density, higher frequency of operation and excessive
leakage power. Moreover, the circuits are usually over-designed to compensate for
uncertainties due to variations. The over-designed circuits not only make timing closure
difficult but also cause excessive power consumption. For portable electronics,
excessive power consumption may reduce battery life; for non-portable systems it
may impose great difficulties in cooling and packaging.
The objective of my research has been to develop design methodologies to address
variations and power dissipation for reliable circuit operation. The proposed work
has been divided into three parts: the first part addresses the issues related with
power/ground noise induced by clock distribution network and proposes techniques to reduce power/ground noise considering the effects of process variations. The second
part proposes an elastic pipeline scheme for random circuits with feedback loops. The
proposed scheme provides a low-power solution that has the same variation tolerance
as the conventional approaches. The third section deals with discrete buffer and wire
sizing for link-based non-tree clock network, which is an energy efficient structure for
skew tolerance to variations.
For the power/ground noise problem, our approach could reduce the peak current
and the delay variations by 50% and 51% respectively. Compared to conventional
approach, the elastic timing scheme reduces power dissipation by 20% − 27%. The
sizing method achieves clock skew reduction of 45% with a small increase in power
dissipation.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-3119 |
| Date | 15 May 2009 |
| Creators | Samanta, Rupak |
| Contributors | Hu, Jiang |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | electronic, application/pdf, born digital |
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