Thesis (M.Sc.Eng.) PLEASE NOTE: Boston University Libraries did not receive an Authorization To Manage form for this thesis or dissertation. It is therefore not openly accessible, though it may be available by request. If you are the author or principal advisor of this work and would like to request open access for it, please contact us at open-help@bu.edu. Thank you. / Cloud computing demands the reconfigurability on a sub-core basis to maximize the performance per customer application and the overall utilization of hardware resources in a data center. We propose the design of arithmetic units (AUs) using look-up tables (LUTs), which can also function as cache units. We imagine such LUT-based implementations of AUs and caches to be part of a malleable computing paradigm that allows the re-configuration of the core architecture inside a core and across cores. Our envisioned malleable computing can configure an LUT to behave as an AU or a cache at run time depending on the customers, their application requirements, and the computational demand in a data-center.
To evaluate the scope for reconfigurability of LUTs, we determined the exchange rate between caches and AUs. This exchange rate tells us the cost of designing a LUT-based AU in kilo bytes of cache. In this thesis, we provide exchange rates for LUT-based adder and multiplier designs. For our analysis, we use CACTI 6.5 to estimate the access time, area, and power of caches varying in size, number of banks, and set associativity, which we fitted by multinomial models. The delay time of these LUT-based designs is comparable to that of logic gate based designs of AUs using the logical effort theory for scaling. As delay time for LUT-based AUs we get 0.5 ns to 1.5 ns (2 GHz to 667 MHz) using the 45 nm Nangate open cell library. The cost of an adder ranges from 0.125 kB to 5 kB cache size. The cost for an multiplier ranges from 2.7 kB to 2.8 kB cache size. The area for these LUT-based designs is smaller or equal compared to logic gate based adder and multiplier designs. Using RRAM technology the area can be reduced by two orders of magnitude with a slowdown in delay time by one order of magnitude.
We also compared the robustness of our LUT-based adder and multiplier designs to logic gate equivalent adder and multiplier designs in presence of soft errors using analytical models and simulations. We show that LUT-based designs are more resilient toward soft errors when comparing output error rates of AUs. Our analytical models can help design robust AUs by quantifying design patterns in terms of their robustness. / 2031-01-01
| Identifer | oai:union.ndltd.org:bu.edu/oai:open.bu.edu:2144/21244 |
| Date | January 2014 |
| Creators | Raudies, Florian |
| Publisher | Boston University |
| Source Sets | Boston University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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