Processor design has evolved over the years to take advantage of new
technology and innovative concepts in order to improve performance.
Diminishing returns for improvements based on current techniques
such as exploiting instruction-level parallelism have caused
designers to shift their focus. Rather then focusing on
single-threaded architectures, designers have increasingly sought to
improve system performance and increase overall throughput by
exploiting thread-level parallelism through multithreaded multi-core
architectures.
Software modeling and simulation are common techniques used to aid
hardware design. Through simulation, different architectures can be
explored and verified before hardware is actually built. An
appropriate choice for the level of abstraction can reduce the
complexity and the time required to create and simulate software
models.
The first contribution of this thesis is a transaction-level
simulation model of a multithreaded multi-core processor. The
transaction level is a high level of abstraction that hides
computational details from the designer allowing key architectural
elements to be quickly explored. The processor model that has been
implemented for this thesis is flexible and can be used to explore
various designs by simulating different processor and cache
configurations. The processor model is written in SystemC, which is
a standard design and verification language that is built on C++ and
that can be used to model hardware systems.
The second contribution of this thesis is the development of an
application model that seeks to characterize the behavior of
instruction execution and data accesses in a program. An
application's instruction trace can be profiled to produce a model
that can be used to generate a synthetic trace with similar
characteristics. The synthetic trace can then be used in place of
large trace files to drive the SystemC-based processor model. The
application model can also produce various workload scenarios for
multiprocessor simulation.
From experimentation, various processor configurations and different
workload scenarios were simulated to explore the potential benefits
of a multi-core multithreaded processor architecture. Performance
increased with diminishing returns with additional multi-core
multithreading support. However, these improvement were limited by
the utilization of the shared bus. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-08-09 11:45:46.749
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OKQ.1974/510 |
| Date | 13 August 2007 |
| Creators | Ma, Nicholas |
| Contributors | Queen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.)) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | 11804379 bytes, application/pdf |
| Rights | This publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner. |
| Relation | Canadian theses |
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