Coarse-grained fabrics are comprised of multi-bit configurable logic blocks and configurable interconnect. This work is focused on area and energy optimization techniques for coarse-grained reconfigurable fabric architectures. In this work, a variety of design techniques have been explored to improve the utilization of computational resources and increase energy savings. This includes splitting, folding, multi-level vertical interconnect. In addition to this, I have also studied fully connected homogeneous and heterogeneous architectures, and 3D architecture. I have also examined some of the hybrid strategies of computation unit’s arrangements. In order to perform energy and area analysis, I selected a set of signal and image processing benchmarks from MediaBench suite. I implemented various fabric architectures on 90nm ASIC process from Synopsys. Results show area improvement with energy savings as compared to baseline architecture.
Identifer | oai:union.ndltd.org:unt.edu/info:ark/67531/metadc103413 |
Date | 12 1900 |
Creators | Yadav, Anil |
Contributors | Mehta, Gayatri, Namuduri, Kamesh, Gomathisankaran, Mahadevan |
Publisher | University of North Texas |
Source Sets | University of North Texas |
Language | English |
Detected Language | English |
Type | Thesis or Dissertation |
Format | Text |
Rights | Public, Yadav, Anil, Copyright, Copyright is held by the author, unless otherwise noted. All rights Reserved. |
Page generated in 0.0016 seconds