This master thesis is concerned about the resynthesis of combinational circuits with the help of evolutional principles. The first part of this text describes logic synthesis and its weak spots, evolutional synthesis and its advantages, and also some of the existing synthesis programs. The second part shows usage of graph algorithms in logic synthesis and their possible usage in an extension for the chosen synthesis program. Suggested design and practical implementation of the extension is also described in this part. In the third part extension testing is mentioned. The fourth part is the last one and concludes gained knowledge and results.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:363902 |
| Date | January 2017 |
| Creators | Kocnová, Jitka |
| Contributors | Sekanina, Lukáš, Vašíček, Zdeněk |
| Publisher | Vysoké učení technické v Brně. Fakulta informačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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