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Design of Bus-based Communication Architectures for Systems with Throughput Constraints

Modern system-on-chip consists of an increasing number of highly complex modules. The quality of the interfaces and throughput of communication connections between these components are crucial to the performance of the system, since communication is often the main bottleneck in modern application domains like multimedia.
In this thesis, a bus-based communication architecture synthesis approach is proposed. Given the result of hardware/software partitioning and pipelined scheduling, the proposed approach constructs a communication topology which meets the constraints. We begin with the minimum number of AHB and an APB, each time we add an AHB and do some transformation such as merging or setting local buses. Our goal is to find the bus architecture which has minimum area. We use integer programming to construct a bus architecture each time, until the bus architecture with the minimum area are found. By this approach, we can save a lot of time required to design the communication architecture manually.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0801105-100013
Date01 August 2005
CreatorsLiao, Ren-Zheng
ContributorsPei-yin Chen, Yun-nan Chang, Jer-min Jou, Shen-fu Siao, Shiann-rong Kuang
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801105-100013
Rightsnot_available, Copyright information available at source archive

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