The robust symmetrical number system (RSNS) can play a significant role in the reduction of encoding errors within a low-power folding analog-to-digital converter (ADC). A key part of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary output. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli 1 7 m =, 2 8 m = and 3 9 m = (ADC dynamic range M = 126). Also described is a pipelined digital logic implementation for use in high speed programmable logic or application specific integrated circuits. To verify correct outputs of the robust symmetrical residue-to-binary conversion algorithm, a digital test circuit is described that generates the thermometer code (symmetrical residues) for the 3-channel ADC design.
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/1762 |
| Date | 12 1900 |
| Creators | Monta, Ross Alan |
| Contributors | Pace, Phillip E., Fouts, Douglas, Naval Postgraduate School (U.S.)., Department of Electrical and Computer Engineering |
| Publisher | Monterey, California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xvi, 67 p. : ill. (some col.) ;, application/pdf |
| Rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted. |
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