The OpenSPARC T1 is a multithreading processor developed and open sourced by Sun Microsystems (now Oracle). This paper presents an implementation of the low-power Tagless-Hit Instruction Cache (TH-IC) for the T1, after adapting it to the multithreading architecture found in that processor. The TH-IC eliminates the need for many instruction cache and ITLB accesses, by guaranteeing that accesses within a much smaller L0-style cache will hit. The OpenSPARC T1 uses a 16KB, 4-way set associative instruction, and a 64-entry fully associative ITLB. The addition of the TH-IC eliminates approximately 75% of accesses to these structures, instead processing the fetch directly from a much smaller 128 byte data array. Adding the TH-IC to the T1 also demonstrates that even already power efficient processors can be made more efficient using this technique. / A Thesis submitted to the Department of Computer Science in partial fulfillment of
the requirements for the degree of Master of Science. / Degree Awarded: Fall Semester, 2010. / Date of Defense: October 29, 2010. / Simultaneous Multithreading, Low Power / Includes bibliographical references. / Gary Tyson, Professor Directing Thesis; David Whalley, Committee Member; Xin Yuan, Committee Member.
| Identifer | oai:union.ndltd.org:fsu.edu/oai:fsu.digital.flvc.org:fsu_168213 |
| Contributors | Gavin, Peter Brendan (authoraut), Tyson, Gary (professor directing thesis), Whalley, David (committee member), Yuan, Xin (committee member), Department of Computer Science (degree granting department), Florida State University (degree granting institution) |
| Publisher | Florida State University |
| Source Sets | Florida State University |
| Language | English, English |
| Detected Language | English |
| Type | Text, text |
| Format | 1 online resource, computer, application/pdf |
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