The arithmetic operations in most digital system are in the conventional binary number systems. However, the finite field arithmetic has also been widely used in applications of cryptography and communication channel coding. For example, finite field constant multiplication is applied to the advanced encryption standard (AES) and in the Reel-Solomon code. In this thesis, we develop a synthesizer that can automatically generate optimized gate-level netlists for constant matrix multiplication in Galois Field GF(2^n). The logic minimization is based on the a new common-factor elimination (CSE) algorithm that can efficiently finds the shared common factors among all the bit-level Boolean equations. Both the area and speed performance are considered during the logic optimization process. Experimental results show that the synthesized circuits have better area and/or speed performance compared with those obtained using Synopsys logic synthesis tools.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0712104-074200 |
| Date | 12 July 2004 |
| Creators | Tu, Chia-Shin |
| Contributors | Wei-Chin Hsu, Yun-Nan Chang, Chien-Hsing Wu, Shen-Fu Hsiao, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712104-074200 |
| Rights | unrestricted, Copyright information available at source archive |
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