In this paper we present a dataflow processor
architecture based on [1], which is driven by controlflow
generated tokens. We will show the special properties of
this architecture with regard to scalability, extensibility,
and parallelism. In this context we outline the application
scope and compare our approach with related work.
Advantages and disadvantages will be discussed and we
suggest solutions to solve the disadvantages. Finally an
example of the implementation of this architecture will be
given and we have a look at further developments.
We believe the features of this basic approach predestines
the architecture especially for embedded systems and
system on chips.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa.de:swb:ch1-200700950 |
| Date | 08 June 2007 |
| Creators | Moser, Nico, Gremzow, Carsten, Menge, Matthias |
| Contributors | TU Chemnitz, Fakultät für Informatik |
| Publisher | Universitätsbibliothek Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:conferenceObject |
| Format | application/pdf, text/plain, application/zip |
| Relation | dcterms:isPartOfhttp://nbn-resolving.de/urn:nbn:de:swb:ch1-200700815 |
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