Abstract
A 10-bit 1MSample/sec successive approximation A/D converter is described in this thesis. First, by a comparator designed with high input impedance is used for the load of the modified wide-swing R-2R D/A converter. The modified wide-swing R-2R D/A converter possesses a high impedance load thus the op-amp is used in the D/A converter can be neglected. Therefore, the usable swing range and the convertible speed are improved and the power consumption is reduced. Secondary, the modified wide-swing R-2R D/A converter that contains modified switch-circuit and matched-component is used to obtain the good voltage division thereby improving the accuracy. Finally, the modified timing skew-insensitive double-sampling S/H circuit is used to sample a high precision signal to the comparator. This modified timing skew-insensitive double-sampling S/H circuit consists of high-gain high-swing op-amp, CMOS dummy switches, and timing skew-insensitive technique for upgrading the precision and swing range. By using these improved circuits the overall speed, accuracy and swing range are improved.
The proposed successive approximation A/D converter is designed by TSMC 1P4M 0.35£gm CMOS process, and it operates at 3.3V power supply voltage with 0.8 to 2.9V reference voltage. The simulation results show that DNL is 0.5LSB, INL is 1LSB, and the power consumption is 8mW.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0718103-092820 |
| Date | 18 July 2003 |
| Creators | Lin, Chun-Yao |
| Contributors | Shyh-Jye Jou, Jinn-Shyan Wang, Jyi-Tsong Lin, Chia-Hsiung Kao, Yao-Tsung Tsai |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718103-092820 |
| Rights | not_available, Copyright information available at source archive |
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