Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.
| Identifer | oai:union.ndltd.org:unt.edu/info:ark/67531/metadc12079 |
| Date | 12 1900 |
| Creators | Bani, Ruchi Rastogi |
| Contributors | Mohanty, Saraju P., Kougianos, Elias, Mikler, Armin R. |
| Publisher | University of North Texas |
| Source Sets | University of North Texas |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
| Format | Text |
| Rights | Public, Copyright, Bani, Ruchi Rastogi, Copyright is held by the author, unless otherwise noted. All rights reserved. |
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