A VLSI system for image compression based on two dimensional discrete cosine transform
(2-D DCT) is designed and its performance is estimated. The focus is mainly on the reduction
of power consumption and a reasonable speed. A 2-D DCT algorithm called row-column
decomposition is chosen for the VLSI design of the system. Then a modified power
saving architecture is proposed based on the property and purpose of image compression.
Several methods, including the use of low power library cells and low voltage (Vdd=1.5v),
are used to achieve the goal of power reduction. Techniques that reduces power, such as ordering
of input signals and common term sharing, are applied to the design of the system.
These techniques and methods span from algorithm, architecture, logic style and circuit. In
addition to using standard cells, some custom cells are also created. The control, timing and
synchronization circuitry is detailed in the design of the system. HSPICE simulation shows
that the designed 2-D DCT system can operate at more than 20MHz for 8 by 8 image blocks
using 1.2u CMOS technology. Based on the effective switched capacitances provided by
library cell data sheets, power consumption performance is estimated. The system consumes
about 17mW at the maximum speed and the specified supply voltage. Comparisons to other
implementations show that the designed system exceeds in power performance. / Graduation date: 1996
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/34695 |
| Date | 18 March 1996 |
| Creators | Li, Quanrong |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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