Modern digital designs require high performance and low cost. In this scenario, timing
analysis is an essential step for each phase of the integrated circuit design cycle. To minimize
the design turn-around time, the ability to correctly predict the timing behavior of the
chip is extremely important. This has resulted in a demand for techniques to perform an
accurate timing analysis.
A number of existing timing analysis approaches are available. Most of these are pessimistic
in nature due because of some inherent inaccuracies in the modeling of the timing
behavior of logic gates. Although some techniques use accurate gate delay models, they
have only been used to calculate the longest sensitizable delay or the shortest topological
path delay for the circuit. In this work, a procedure to and the shortest destabilizing delay,
as well as the longest sensitizable delay of a static CMOS circuit is developed. This procedure
is also able to determine the exact circuit path as well as the input vector transition for
which the shortest destabilizing (or longest sensitizable) delay can be achieved.
Over a number of examples, on an average, the minimum destabilizing delay results in
an improvement of 24% as compared to the minimum static timing analysis approach. The
maximum sensitizable timing analysis results in an improvement of 7% over sensitizable
timing analysis with pin-to-output delays. Therefore, the results show that the pessismism
in timing analysis can be considerably decreased by using data dependent gate delays for
maximum as well as minimum sensitizable timing analysis.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/5948 |
| Date | 17 September 2007 |
| Creators | Singh, Karandeep |
| Contributors | Khatri, Sunil P |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | 332915 bytes, electronic, application/pdf, born digital |
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