System-on-a-Chip (SoC) is a trend to achieve high performance, low cost, and low power in modern electronic devices. As the demand of functionality and performance increase, more IPs (Intellectual Property) are integrated into a modern SoC. Developing such a complex SoC is challenging since the SoC has limited observability; modern SoCs usually leave limited spared I/O pins for debugging purpose due to cost consideration, making it hard to analyze the internal activities via the limited I/O pins. This hampers the SoC development. To ease the difficulty, we have implemented the SYS-SIP (National Sun Yat-Sen university's SoC Infrastructure IP's) to enable the SoC development in terms of verification, debugging, monitor
ing, and performance tuning. The SYS-SIP consists of five members: Processor External Interrupt Verification Module (PEVM), ICE, processor tracer, bus tracer, and protocol checker. Each of them serves specific purposes in verification, debugging, monitoring, and performance tuning. The SYS-SIP can be applied at diffierent design stages: RTL, FPGA, and chip level. The results show that SYS-SIP eases the SoC development and shortens the time-to-market significantly.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-1012109-151215 |
| Date | 12 October 2009 |
| Creators | Yang, Fu-Ching |
| Contributors | Chua-Ching Wang, Ing-Jer Huang, Kuen-Jong Lee, Jiun-In Guo, Cheng-Wen Wu, Jing-Yang Jou |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1012109-151215 |
| Rights | off_campus_withheld, Copyright information available at source archive |
Page generated in 0.0016 seconds