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An Analytical Model for On-Chip Interconnects in Multimedia Embedded Systems

No / The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects. Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection network under bursty multimedia traffic and nonuniform message destinations. Extensive simulation experiments are conducted to validate the accuracy of the model, which is then adopted as a cost-efficient tool to investigate the effects of bursty multimedia traffic with nonuniform destinations on the network performance.

Identiferoai:union.ndltd.org:BRADFORD/oai:bradscholars.brad.ac.uk:10454/9754
Date January 2013
CreatorsWu, Y., Min, Geyong, Zhu, D., Yang, L.T.
Source SetsBradford Scholars
Detected LanguageEnglish
TypeArticle, No full-text available in the repository

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