In recent years ternary reversible logic has caught the attention of researchers because of its
enormous potential in different fields, in particular quantum computing. It is desirable that
any future reversible technology should be fault tolerant and have low power consumption;
hence developing testing techniques in this area is of great importance.
In this work we propose a design for an online testable ternary reversible circuit. The
proposed design can implement almost all of the ternary logic operations and is also capable
of testing the reversible ternary network in real time (online). The error detection unit is
also constructed in a reversible manner, which results in an overall circuit which meets
the requirements of reversible computing. We have also proposed an upgrade of the initial
design to make the design more optimized. Several ternary benchmark circuits have been
implemented using the proposed approaches. The number of gates required to implement
the benchmarks for each approach have also been compared. To our knowledge this is the
first such circuit in ternary with integrated online testability feature. / xii, 92 leaves : ill. ; 29 cm
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:ALU.w.uleth.ca/dspace#10133/3208 |
| Date | January 2011 |
| Creators | Rahman, Md. Raqibur |
| Contributors | Rice, Jacqueline E |
| Publisher | Lethbridge, Alta. : University of Lethbridge, c2011, Arts and Science, Department of Mathematics and Computer Science |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | Thesis (University of Lethbridge. Faculty of Arts and Science) |
Page generated in 0.0019 seconds