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Improved Subset Generation For The MU-Decoder

The MU-Decoder is a hardware subset generator that finds use in partial reconfiguration
of FPGAs and in numerous other applications. It is capable of generating a set S of subsets
of a large set Z_n with n elements. If the subsets in S satisfy the isomorphic totally-
ordered property, then the MU-Decoder works very efficiently to produce a set of u subsets in O(log n) time and Θ(n √u log n) gate cost. In contrast, a vain approach requires Θ(un)
gate cost. We show that this low cost for the MU-Decoder can be achieved without the isomorphism constraint, thereby allowing S to include a much wider range of subsets. We also show that if additional constraints on the relative sizes of the subsets in S can be placed, then u subsets can be generated with Θ(n √u) cost. This uses a new hardware enhancement proposed in this thesis. Finally, we show that by properly selecting S and by using some elements of traditional methods, a set of Θ (un^log( log (n/log n))) subsets can be produced with Θ(n √u) cost.

Identiferoai:union.ndltd.org:LSU/oai:etd.lsu.edu:etd-02072017-185004
Date21 February 2017
CreatorsAgarwal, Utsav
ContributorsBusch, Konstantin (Costas), Trahan, Jerry, Vaidyanathan, Ramachandran
PublisherLSU
Source SetsLouisiana State University
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lsu.edu/docs/available/etd-02072017-185004/
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