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Optimising fault modelling and test development for VLSI analogue circuits

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1. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503

Identifer	oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:288503
Date	January 2001
Creators	Besnard, Stéphane Claude Louis
Publisher	University of Huddersfield
Source Sets	Ethos UK
Detected Language	English
Type	Electronic Thesis or Dissertation