<p>All large-scale digital Integrated Circuits need an appropriate strategy for clocking and synchronization. In large-scale and high-speed System-on-Chips (SoC), the traditional"Globally Synchronous"(GS) approach is not longer viable, due to severe wire delays. Instead new solutions as"Globally Synchronous, Locally Asynchronous"(GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this work, such an approach together with a circuit solution in 0.18mm CMOS process has been presented. This solution allows clocking frequencies up to 4 GHz.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-2117 |
| Date | January 2004 |
| Creators | Mesgarzadeh, Behzad |
| Publisher | Linköping University, Department of Electrical Engineering, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
| Relation | LiTH-ISY-Ex, ; 3438 |
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