The sustained demand for faster,more powerful chips has beenmet by the
availability of chip manufacturing processes allowing for the integration
of increasing numbers of computation units onto a single die. The resulting
outcome, especially in the embedded domain, has often been called
SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC).
MPSoC design brings to the foreground a large number of challenges,
one of the most prominent of which is the design of the chip interconnection.
With a number of on-chip blocks presently ranging in the tens, and
quickly approaching the hundreds, the novel issue of how to best provide
on-chip communication resources is clearly felt.
NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable
answer to this design concern. By bringing large-scale networking
concepts to the on-chip domain, they guarantee a structured answer to
present and future communication requirements. The point-to-point connection
and packet switching paradigms they involve are also of great help
in minimizing wiring overhead and physical routing issues.
However, as with any technology of recent inception, NoC design is
still an evolving discipline. Several main areas of interest require deep
investigation for NoCs to become viable solutions:
• The design of the NoC architecture needs to strike the best tradeoff
among performance, features and the tight area and power constraints
of the on-chip domain.
• Simulation and verification infrastructure must be put in place to
explore, validate and optimize the NoC performance.
• NoCs offer a huge design space, thanks to their extreme customizability
in terms of topology and architectural parameters. Design
tools are needed to prune this space and pick the best solutions.
• Even more so given their global, distributed nature, it is essential to
evaluate the physical implementation of NoCs to evaluate their suitability
for next-generation designs and their area and power costs.
This dissertation focuses on all of the above points, by describing a
NoC architectural implementation called ×pipes; a NoC simulation environment
within a cycle-accurate MPSoC emulator called MPARM; a NoC
design flow consisting of a front-end tool for optimal NoC instantiation,
called SunFloor, and a set of back-end facilities for the study of NoC physical
implementations.
This dissertation proves the viability of NoCs for current and upcoming
designs, by outlining their advantages (alongwith a fewtradeoffs) and
by providing a full NoC implementation framework. It also presents some
examples of additional extensions of NoCs, allowing e.g. for increased
fault tolerance, and outlines where NoCsmay find further application scenarios,
such as in stacked chips.
| Identifer | oai:union.ndltd.org:unibo.it/oai:amsdottorato.cib.unibo.it:931 |
| Date | 17 April 2008 |
| Creators | Angiolini, Federico <1978> |
| Contributors | Benini, Luca |
| Publisher | Alma Mater Studiorum - Università di Bologna |
| Source Sets | Università di Bologna |
| Language | English |
| Detected Language | English |
| Type | Doctoral Thesis, PeerReviewed |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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