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TCAD approaches to multidimensional simulation of advanced semiconductor devices

Technology scaling increasingly emphasizes complexity and non-ideality
of the electrical behavior of semiconductor devices and boosts interest on alternatives to the conventional planar MOSFET architecture.
TCAD simulation tools are fundamental to the analysis and development of new technology generations. However, the increasing device
complexity is reflected in an augmented dimensionality of the problems
to be solved. The trade-off between accuracy and computational cost of
the simulation is especially influenced by domain discretization: mesh
generation is therefore one of the most critical steps and automatic approaches are sought. Moreover, the problem size is further increased by
process variations, calling for a statistical representation of the single
device through an ensemble of microscopically different instances. The
aim of this thesis is to present multi-disciplinary approaches to handle
this increasing problem dimensionality in a numerical simulation perspective. The topic of mesh generation is tackled by presenting a new
Wavelet-based Adaptive Method (WAM) for the automatic refinement
of 2D and 3D domain discretizations. Multiresolution techniques and
efficient signal processing algorithms are exploited to increase grid resolution in the domain regions where relevant physical phenomena take
place. Moreover, the grid is dynamically adapted to follow solution
changes produced by bias variations and quality criteria are imposed
on the produced meshes. The further dimensionality increase due to
variability in extremely scaled devices is considered with reference to
two increasingly critical phenomena, namely line-edge roughness (LER)
and random dopant fluctuations (RD). The impact of such phenomena
on FinFET devices, which represent a promising alternative to planar
CMOS technology, is estimated through 2D and 3D TCAD simulations
and statistical tools, taking into account matching performance of single
devices as well as basic circuit blocks such as SRAMs. Several process
options are compared, including resist- and spacer-defined fin patterning as well as different doping profile definitions. Combining statistical
simulations with experimental data, potentialities and shortcomings of
the FinFET architecture are analyzed and useful design guidelines are
provided, which boost feasibility of this technology for mainstream applications in sub-45 nm generation integrated circuits.

Identiferoai:union.ndltd.org:unibo.it/oai:amsdottorato.cib.unibo.it:1124
Date07 April 2008
CreatorsBaravelli, Emanuele <1980>
ContributorsMasetti, Guido
PublisherAlma Mater Studiorum - Università di Bologna
Source SetsUniversità di Bologna
LanguageEnglish
Detected LanguageEnglish
TypeDoctoral Thesis, PeerReviewed
Formatapplication/pdf
Rightsinfo:eu-repo/semantics/openAccess

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